View RT8223A_5607028.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

RT8223A/b 1 ds8223a/b-04 april 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. applications z notebook and sub-notebook computers z 3-cell and 4-cell li+ battery-powered devices high efficiency, main power supply controller for notebook computers general description the RT8223A/b dual step-down, switch-mode power- supply controller generates logic-supply voltages in battery-powered systems. the RT8223A/b includes two pulse-width modulation (pwm) controllers fixed at 5v/ 3.3v or adjustable from 2v to 5.5v. this device also features 2 linear regulators providing fixed 5v and 3.3v outputs. the linear regulator each provides up to 70ma output current with automatic linear-regulator bootstrapping to the pwm outputs. the RT8223A/b includes on-board power-up sequencing, the power good output, internal soft- start, and internal soft-discharge output that prevents negative voltages on shutdown. a constant on-time pwm control scheme operates without sense resistor and provides 100ns response to load transients while maintaining a relatively constant switching frequency. the unique ultrasonic mode maintains the switching frequency above 25khz, which eliminates noise in audio applications. other features include diode- emulation mode (dem), which maximizes efficiency in light-load applications, and fixed-frequency pwm mode, which reduces rf interference in sensitive application features z z z z z wide input voltage range 6v to 25v z z z z z dual fixed 5v/3.3v outputs or adjustable from 2v to 5.5v, 1.5% accuracy z z z z z fixed 3.3v and 5v ldo output : 70ma z z z z z 2v reference voltage 1% : 50 a z z z z z constant on-time control with 100ns load step response z z z z z frequency selectable via tonsel setting z z z z z r ds(on) current sensing and programmable current limit combined with enable control z z z z z selectable pwm, dem, or ultrasonic mode z z z z z internal soft-start and soft-discharge z z z z z high efficiency up to 97% z z z z z 5mw quiescent power dissipation z z z z z thermal shutdown z z z z z rohs compliant and halogen free marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. package type qw : wqfn-24l 4x4 (w-type) lead plating system g : green (halogen free and pb free) z : eco (ecological element with halogen free and pb free) rt8223 pin function a : default b : with enc http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 2 ds8223a/b-04 april 2011 www.richtek.com typical application circuit pin configurations (top view) rt8223b wqfn-24l 4x4 RT8223A wqfn-24l 4x4 for fixed voltage regulator entrip1 fb1 ref tonsel fb2 entrip2 lgate2 vout2 vreg3 boot2 phase2 ugate2 nc vreg5 pgnd skipsel en vin ugate1 lgate1 vout1 pgood boot1 phase1 gnd 1 2 3 4 5 6 78910 12 11 18 17 16 15 14 13 21 20 19 24 22 23 25 entrip1 fb1 ref tonsel fb2 entrip2 lgate2 vout2 vreg3 boot2 phase2 ugate2 enc vreg5 pgnd skipsel en vin ugate1 lgate1 vout1 pgood boot1 phase1 gnd 1 2 3 4 5 6 78910 12 11 18 17 16 15 14 13 21 20 19 24 22 23 25 RT8223A phase1 lgate1 boot1 ugate1 vout1 v o u t 1 5 v vin vreg5 vreg3 pgood gnd 16 exposed pad (25) 19 22 20 21 24 23 17 8 phase2 lgate2 boot2 ugate2 vout2 v o u t 2 q2 l 2 c 7 c 1 3 3 . 3 v r 9 c 8 v i n 1 0 f 1 0 f 0 . 1 f r 1 0 c 1 0 10 11 9 12 7 bsc119 n03s q4 bsc119 n03s 0 r 8 0 c 9 4 . 7 h 2 2 0 f q1 l 1 c 2 c 3 r 4 1 0 f 0 . 1 f r 5 c 4 bsc119 n03s q3 bsc119 n03s 0 r 3 0 c 1 6 . 8 h 2 2 0 f r 7 3 . 9 c 6 0 . 1 f 5 v a l w a y s o n 3 . 3 v a l w a y s o n entrip1 entrip2 1 6 fb2 fb1 2 5 r 1 1 5 0 k r 2 1 5 0 k c 5 4 . 7 f r 6 1 0 0 k p g o o d i n d i c a t o r c 1 2 4 . 7 f ref 3 c 1 1 0 . 2 2 f tonsel skipsel 4 14 f r e q u e n c y c o n t r o l p w m / d e m / u l t r a s o n i c en on off 13 pgnd 15 http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 3 ds8223a/b-04 april 2011 www.richtek.com 5 v rt8223b phase1 lgate1 boot1 ugate1 vout1 v o u t 1 vin vreg5 vreg3 pgood pgnd 16 15 19 22 20 21 24 23 17 8 phase2 lgate2 boot2 ugate2 vout2 v o u t 2 q2 l 2 c 7 c 1 7 3 . 3 v r 9 c 1 2 v i n 1 0 f 1 0 f 0 . 1 f r 1 0 c 1 4 10 11 9 12 7 bsc119 n03s q4 bsc119 n03s 0 r 8 0 c 1 3 4 . 7 h 2 2 0 f q1 l 1 c 2 c 3 r 4 1 0 u f 0 . 1 f r 5 c 4 bsc119 n03s q3 bsc119 n03s 0 r 3 0 c 1 6 . 8 h 2 2 0 f r 7 3 . 9 c 1 0 0 . 1 f 5 v a l w a y s o n 3 . 3 v a l w a y s o n entrip1 entrip2 1 6 r 1 1 5 0 k r 2 1 5 0 k c 9 4 . 7 f r 6 1 0 0 k p g o o d i n d i c a t o r c 1 6 4 . 7 f ref 3 c 1 5 0 . 2 2 f tonsel skipsel 4 14 f r e q u e n c y c o n t r o l en on off 13 enc 18 fb2 fb1 2 5 exposed pad (25) gnd p w m / d e m / u l t r a s o n i c on off http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 4 ds8223a/b-04 april 2011 www.richtek.com for adjustable voltage regulator RT8223A phase1 lgate1 boot1 ugate1 vout1 v o u t 1 5 v vin vreg5 vreg3 pgood gnd 16 exposed pad (25) 19 22 20 21 24 23 17 8 phase2 lgate2 boot2 ugate2 vout2 v o u t 2 q2 l 2 c 7 c 1 3 3 . 3 v r 9 c 8 v i n 1 0 f 1 0 f 0 . 1 f r 1 0 c 1 0 10 11 9 12 7 bsc119 n03s q4 bsc119 n03s 0 r 8 0 c 9 4 . 7 h 2 2 0 f q1 l 1 c 2 c 3 r 4 1 0 f 0 . 1 f r 5 c 4 bsc119 n03s q3 bsc119 n03s 0 r 3 0 c 1 6 . 8 h 2 2 0 f r 7 3 . 9 c 6 0 . 1 f 5 v a l w a y s o n 3 . 3 v a l w a y s o n entrip1 entrip2 1 6 fb2 fb1 2 5 r 1 1 5 0 k r 2 1 5 0 k c 5 4 . 7 f r 6 1 0 0 k p g o o d i n d i c a t o r c 1 2 4 . 7 f ref 3 c 1 1 0 . 2 2 f tonsel skipsel 4 14 f r e q u e n c y c o n t r o l p w m / d e m / u l t r a s o n i c en on off 13 r 1 3 6 . 5 k r 1 4 1 0 k c 1 7 c 1 6 0 . 1 f r 1 1 1 5 k r 1 2 1 0 k c 1 4 c 1 5 0 . 1 f pgnd 15 5 v rt8223b phase1 lgate1 boot1 ugate1 vout1 v o u t 1 vin vreg5 vreg3 pgood pgnd 16 15 19 22 20 21 24 23 17 8 phase2 lgate2 boot2 ugate2 vout2 v o u t 2 q2 l 2 c 7 c 1 7 3 . 3 v r 9 c 1 2 v i n 1 0 f 1 0 f 0 . 1 f r 1 0 c 1 4 10 11 9 12 7 bsc119 n03s q4 bsc119 n03s 0 r 8 0 c 1 3 4 . 7 h 2 2 0 f q1 l 1 c 2 c 3 r 4 1 0 f 0 . 1 f r 5 c 4 bsc119 n03s q3 bsc119 n03s 0 r 3 0 c 1 6 . 8 h 2 2 0 f r 7 3 . 9 c 1 0 0 . 1 f 5 v a l w a y s o n 3 . 3 v a l w a y s o n entrip1 entrip2 1 6 r 1 1 5 0 k r 2 1 5 0 k c 9 4 . 7 f r 6 1 0 0 k p g o o d i n d i c a t o r c 1 6 4 . 7 f ref 3 c 1 5 0 . 2 2 f tonsel skipsel 4 14 f r e q u e n c y c o n t r o l en on off 13 enc 18 fb2 fb1 2 5 exposed pad (25) gnd p w m / d e m / u l t r a s o n i c r 1 3 6 . 5 k r 1 4 1 0 k c 2 1 c 2 0 0 . 1 f r 1 1 1 5 k r 1 2 1 0 k c 1 8 c 1 9 0 . 1 f on off http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 5 ds8223a/b-04 april 2011 www.richtek.com function block diagram function block diagram pwm controller (one side) smps2 pwm buck controller boot2 ugate2 phase2 lgate2 gnd vreg5 vout2 fb2 entrip2 pgood smps1 pwm buck controller boot1 ugate1 phase1 lgate1 vreg5 vout1 fb1 entrip1 vreg5 thermal shutdown ref sw threshold tonsel skipsel vin vreg5 pgnd power-on sequence clear fault latch en vreg3 sw threshold ref vreg3 enc trig q t off 1-shot trig q 1-shot r t on + - comp - + fault latch + - + - 1.1 x v ref 0.6 x v ref + - 0.9 x v ref over-voltage under-voltage on-time compute vin tonsel vout ref fb pgood lgate ugate + - blanking time + - vreg5 + - current limit zero detector skipsel phase entrip ss time 25khz detector + + - - s http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 6 ds8223a/b-04 april 2011 www.richtek.com functional pin description entrip1 (pin 1) channel 1 enable and current limit setting input. connect a resistor to gnd to set the threshold for channel 1 synchronous r ds(on) sense. the gnd ? phase1 current- limit threshold is 1/10th the voltage seen at entrip1 over a 0.5v to 2v range. there is an internal 10 a current source from vreg5 to entrip1. fb1 (pin 2) smps1 feedback input. connect fb1 to vreg5 or gnd for fixed 5v operation. or connect fb1 to a resistive voltage- divider from vout1 to gnd to adjust output from 2v to 5.5v. ref (pin 3) 2v reference output. bypass to gnd with a 0.22 f capacitor. ref can source up to 50 a for external loads. loading ref degrades fbx and output accuracy according to the ref load regulation error. tonsel (pin 4) frequency selectable input for vout1/vout2 respectively. 400khz/500khz : connect to vreg5 or vreg3 300khz/375khz : connect to ref 200khz/250khz : connect to gnd fb2 (pin 5) smps2 feedback input. connect fb2 to vreg5 or gnd for fixed 3.3v operation. or connect fb2 to a resistive voltage-divider from vout2 to gnd to adjust output from 2v to 5.5v. entrip2 (pin 6) channel 2 enable and current limit setting input. connect a resistor to gnd to set the threshold for channel 2 synchronous r ds(on) sense. the gnd ? phase2 current limit threshold is 1/10th the voltage seen at entrip2 over a 0.5v to 2v range. there is an internal 10 a current source from vreg5 to entrip2. vout2 (pin 7) smps2 output voltage sense input. connect to the smps2 output. vout2 is an input to the on-time one shot circuit. it also serves as the smps2 feedback input in fixed voltage mode. vreg3 (pin 8) 3.3v linear regulator output. boot2 (pin 9) boost flying capacitor connection for smps2. connect to an external capacitor according to the typical application circuits. ugate2 (pin 10) high-side mosfet floating gate driver output for smps2. ugate2 swings between phase2 and boot2. phase2 (pin 11) inductor connection for smps2. phase2 is the internal lower supply rail for the ugate2 high side gate driver. phase2 is also the current-sense input for the smps2. lgate2 (pin 12) smps2 synchronous-rectifier gate-drive output. lgate2 swings between pgnd and vreg5. en (pin 13) master enable input. the ref/vreg5/vreg3 are enabled if it is within logic high level and disabled if it is less than the logic low level. skipsel (pin 14) operation mode selectable input. ultrasonic mode : connect to vreg5 or vreg3 diode emulation mode : connect to gnd pwm mode : connect to ref gnd [exposed pad (25)] analog ground for smps controller. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 7 ds8223a/b-04 april 2011 www.richtek.com pgnd (pin 15) power ground for smps controller. connect pgnd externally to the underside of the exposed pad. vin (pin 16) high voltage power supply input for 5v/3.3v ldo and feed-forward on-time circuitry. vreg5 (pin 17) 5v linear regulator output.vreg5 is also the supply voltage for the low-side mosfet driver and analog supply voltage for the device. nc (pin 18) (RT8223A) no internal connection. enc (pin 18) (rt8223b) smpsx enable input. pull up to vreg3 or vreg5 to turn on both switcher channels. short to gnd to shutdown them. lgate1 (pin 19) smps1 synchronous rectifier gate drive output. lgate1 swings between pgnd and vreg5. phase1 (pin 20) inductor connection for smps1. phase1 is the internal lower supply rail for the ugate1 high side gate driver. phase1 is also the current sense input for the smps1. ugate1 (pin 21) high-side mosfet floating gate driver output for smps1. ugate1 swings between phase1 and boot1. boot1 (pin 22) boost flying capacitor connection for smps1. connect to an external capacitor according to the typical application circuits. pgood (pin 23) power good output for channel 1 and channel 2. (logical and) vout1 (pin 24) smps1 output voltage-sense input. connect to the smps1 output. vout1 is an input to the on-time one shot circuit. it also serves as the smps1 feedback input in fixed-voltage mode. http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 8 ds8223a/b-04 april 2011 www.richtek.com absolute maximum ratings (note 1) z vin, en to gnd -------------------------------------------------------------------------------------------------------------- ? 0.3v to 30v z phasex to gnd dc -------------------------------------------------------------------------------------------------------------------------- ----- ? 0.3v to 30v < 20ns ---------------------------------------------------------------------------------------------------------------------- --- ? 8v to 38v z bootx to phasex --------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z entripx, skipsel, tonsel, pgood, to gnd ------------------------------------------------------------------- ? 0.3v to 6v z vreg5, vreg3, fbx, voutx, enc, ref to gnd ---------------------------------------------------------------- ? 0.3v to 6v z ugatex to phasex dc -------------------------------------------------------------------------------------------------------------------------- ----- ? 0.3v to 6v < 20ns ---------------------------------------------------------------------------------------------------------------------- --- ? 5v to 7.5v z lgatex to gnd dc -------------------------------------------------------------------------------------------------------------------------- ----- ? 0.3v to 6v < 20ns ---------------------------------------------------------------------------------------------------------------------- --- ? 2.5v to 7.5v z power dissipation, p d @ t a = 25 c wqfn-24l 4x4 -------------------------------------------------------------------------------------------------------------- 1. 923w z package thermal resistance (note 2) wqfn-24l 4x4, ja --------------------------------------------------------------------------------------------------------- 52 c/w wqfn-24l 4x4, jc -------------------------------------------------------------------------------------------------------- 7 c/w z lead temperature (soldering, 10 sec.) --------------------------------------------------------------------------------- 260 c z junction temperature ------------------------------------------------------------------------------------------------------- 150 c z storage temperature range ---------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ------------------------------------------------------------------------------------------------ 2kv mm (ma chine mode) -------------------------------------------------------------------------------------------------------- 200v recommended operating conditions (note 4) z input voltage, v in ------------------------------------------------------------------------------------------------------------ 6v to 25v z junction temperature range ---------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ---------------------------------------------------------------------------------------------- ? 40 c to 100 c http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 9 ds8223a/b-04 april 2011 www.richtek.com electrical characteristics (v in = 12v, en = enc = 5v, entrip1 = entrip2 = 2v, no load on vreg5, vreg3, vout1, vout2 and ref, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit input supply vin standby supply current i vin_sby v in = 6v to 25v, both smps off, en = 5v, enc = gnd -- 200 -- a vin shutdown supply current i vin_shdh v in = 6v to 25v, entripx = en = gnd -- 20 40 a quiescent power consumption both smpss on, fbx = skipsel = ref v out1 = 5.3v, v out2 = 3.5v (note 5) -- 5 7 mw smps output and fb voltage vout1 output voltage in fix ed mode v out1 v in = 6v to 25v, fb1= ref or 5v, skipsel = ref 4.975 5.05 5.125 v vout2 output voltage in fix ed mode v out2 v in = 6v to 25v, fb2 = ref or 5v, skipsel = ref 3.285 3.33 3.375 v fbx in output adjustable mode fbx v in = 6v to 25v 1.975 2 2.025 v output voltage adjustment range v out x smps1, smps2 2 -- 5.5 v fbx adjustable-mode threshold voltage fixed or adj-mode comparator threshold 0.2 0.4 0.55 v eit her smps, skipsel = ref, 0 to 5a -- ? 0.1 -- eit her smps, skipsel = vreg5, 0 to 5a -- ? 1.7 -- dc load regulation v load eit her smps, skipsel = gnd, 0 to 5a -- ? 1.5 -- % line regulation v line either smps, v in = 6v to 25v -- 0.005 -- %/v on time v out1 = 5.05v 1895 2105 2315 tonsel = gnd v out2 = 3.33v 999 1110 1221 v out1 = 5.05v 1227 1403 1579 tonsel = ref v out2 = 3.33v 647 740 833 v out1 = 5.05v 895 1052 1209 on-time pulse width t ugatex tonsel = vreg5 v out2 = 3.33v 475 555 635 ns minimum off-time t lgatex 200 300 400 ns ultrasonic mode frequency skipsel = vreg5 or vreg3 20 28 -- khz soft start soft-start time t ssx zero to full limit from entripx enable -- 2 -- ms current sense current limit threshold (default) v entri px = vreg5, gnd ? phasex 180 200 220 mv entripx source current i entripx v entri px = 0.9v 9.4 10 10.6 a entripx current temperature coefficient tc ientripx -- 1600 -- ppm/ c entripx adjustment range v entri px = i entri px x r entri px 0.5 -- 2 v to be continued http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 10 ds8223a/b-04 april 2011 www.richtek.com to be continued parameter symbol test conditions min typ max unit current limit threshold gnd ? phasex, v entripx =2v 180 200 220 mv zero-current threshold skipsel = vreg5 or gnd, gnd ? phasex -- 3 -- mv internal regulator and reference vreg5 output voltage v vreg5 v out1 = gnd, 6v < v in < 25v, 0 < i vreg5 < 70ma 4.8 5 5.2 v vreg3 output voltage v vreg3 v out2 = gnd, 6v < v in < 25v, 0 < i vreg3 < 70ma 3.2 3.33 3.46 v vreg5 short current i vreg5 vreg5 = gnd, v out1 = gnd -- 175 275 ma vreg3 short current i vreg3 vreg3 = gnd, v out2 = gnd -- 175 275 ma vreg5 switchover threshold to v out1 rising edge at v out1 regulation point 4.53 4.66 4.79 v vreg3 switchover threshold v sw3 rising edge at v out2 regulation point, hysteresis = 6% 2.98 3.08 3.18 v vregx switchover equivalent resistance r sw vregx to v outx , 10ma -- 1.5 3 ref output voltage v re f no external load 1.98 2 2.02 v ref load regulation 0 < i load < 50ua -- 10 -- mv ref sink current ref in regulation 5 -- -- a uvl o vreg3 uvlo threshold smpsx off -- 2.5 -- v rising edge -- 4.35 4.5 v vreg5 uvlo threshold falling edge 3.9 4.05 4.25 v power good pgood detect (fbx rising edge) ? 11 ? 7.5 ? 4 pgood threshold v pgoodx hysteresis -- 8 -- % pgood propagation delay falling edge, 50mv overdrive -- 10 -- s pgood leakage current high state, forced to 5.5v -- -- 1 a pgood output low voltage i sink = 4ma -- -- 0.3 v fault detection ovp trip threshold v fb_ov p fbx with respect to internal reference 108 111 115 % ovp propagation delay -- 10 -- s uvp detect (fbx falling edge) 46 52 58 uvp trip threshold v uv hysteresis -- 8 -- % uvp shutdown blanking time t shdn_uvp from entripx enable -- 3 -- ms thermal shutdown thermal shutdown t shdn -- 150 -- c thermal shutdown hysteresis -- 10 -- c di sch arge voutx discharge current i disx entripx = enc = 0v, v outx = 0.5v 10 60 -- ma vregx discharge current en = 0v, vregx = 0.5v 2.5 -- -- ma http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 11 ds8223a/b-04 april 2011 www.richtek.com parameter symbol test conditions min typ max unit logic input low level (internal fixed voutx) -- -- 0.2 fb1/fb2 input voltage high level (internal fixed voutx) 4.5 -- -- v low level (dem mode) -- -- 0.8 ref level (pwm mode) 1.8 -- 2.3 skipsel input voltage high level (ultrasonic mode) 2.7 -- -- v low level (smpss off) -- -- 0.35 on level (smpss on) 0.5 -- 2 entripx input voltage v entri px high level (smpss off) 4.5 -- -- v shutdown -- -- 0.4 enable 2.4 -- -- en voltage v en open 2.4 3.3 4.2 v v en = 0.2v (source) 1 3 5 en current i en v en = 3.3v (sink) -- 3 8 a shutdown -- -- 0.6 enc threshold voltage (rt8223b) v enc enable 2 -- -- v v out1 /v out2 = 200khz/250khz -- -- 0.8 v out1 /v out2 = 300khz/375khz 1.8 -- 2.3 tonsel setting voltage v out1 /v out2 = 400khz/500khz 2.7 -- -- v tonsel, skipsel = 0v or 5v ? 1 -- 1 input leakage current enc = 0v or 5v (rt8223b) ? 1 -- 1 a internal boot switch internal boost charging switch on-resistance vreg5 to bootx -- 20 -- power mosfet drivers ugatex, high state -- 3 6 ugatex on-resistance ugatex, low state -- 1.5 4 lgatex, high state -- 2.2 5 lgatex on-resistance lgate x, low state -- 0.6 1.5 lgatex rising -- 30 -- dead time ugatex rising -- 40 -- ns note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case positions of jc are on the lead of the sop package and the expose pad for the sop(exposed pad) package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. p vin + p vreg5 http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 12 ds8223a/b-04 april 2011 www.richtek.com typical operating characteristics v out2 output efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) dem mode ultrasonic mode pwm mode v in = 8v, tonsel = gnd, en = v in , entrip1 = gnd, entrip2 = 0.91v v out1 output efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) v out2 output efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) dem mode ultrasonic mode pwm mode v in = 12v, tonsel = gnd, en = v in , entrip1 = gnd, entrip2 = 0.91v, v out1 output efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) dem mode ultrasonic mode pwm mode v in = 12v, tonsel = gnd, en = v in , entrip1 = 0.91v, entrip2 = gnd v out1 output efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) dem mode ultrasonic mode pwm mode v in = 20v, tonsel = gnd, en = v in , entrip1 = 0.91v, entrip2 = gnd v out2 output efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) dem mode ultrasonic mode pwm mode tonsel = gnd, en = v in , entrip1 = gnd, entrip2 = 0.91v v in = 20v dem mode ultrasonic mode pwm mode v in = 8v, tonsel = gnd, en = v in , entrip1 = 0.91v, entrip2 = gnd http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 13 ds8223a/b-04 april 2011 www.richtek.com v out1 output switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) dem mode ultrasonic mode pwm mode v in = 8v, tonsel = gnd, en = v in , entrip1 = 0.91v, entrip2 = gnd v out2 output switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 275 300 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) dem mode ultrasonic mode pwm mode v in = 8v, tonsel = gnd, en = v in , entrip1 = gnd, entrip2 = 0.91v v out1 output switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) dem mode ultrasonic mode pwm mode v in = 12v, tonsel = gnd, en = v in , entrip1 = 0.91v, entrip2 = gnd v out2 output switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 275 300 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) dem mode ultrasonic mode pwm mode v in = 12v, tonsel = gnd, en = v in , entrip1 = gnd, entrip2 = 0.91v v out1 output switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) dem mode ultrasonic mode pwm mode v in = 20v, tonsel = gnd, en = v in , entrip1 = 0.91v, entrip2 = gnd v out2 output switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 275 300 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) dem mode ultrasonic mode pwm mode v in = 20v, tonsel = gnd, en = v in , entrip1 = gnd, entrip2 = 0.91v http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 14 ds8223a/b-04 april 2011 www.richtek.com v ref vs. output current 2.0010 2.0012 2.0014 2.0016 2.0018 2.0020 2.0022 2.0024 2.0026 2.0028 2.0030 -10 0 10 20 30 40 50 output current (ua) v ref (v) v in = 12v, tonsel = gnd, en = v in , entrip1 = entrip2 = gnd vreg3 output voltage vs. output current 3.306 3.308 3.310 3.312 3.314 3.316 3.318 3.320 3.322 3.324 0 10203040506070 output current (ma) output voltage (v) v in = 12v, tonsel = gnd, en = v in , entrip1 = entrip2 = gnd vreg5 output voltage vs. output current 4.960 4.962 4.964 4.966 4.968 4.970 4.972 4.974 4.976 4.978 4.980 0 10203040506070 output current (ma) output voltage (v) v in = 12v, tonsel = gnd, en = v in , entrip1 = entrip2 = gnd battery current vs. input voltage 0.1 1 10 100 7 9 11 13 15 17 19 21 23 25 input voltage (v) battery current (ma) dem mode ultrasonic mode pwm mode no load, tonsel = gnd, en = v in , entrip1 = entrip2 = 0.91v v out2 output voltage vs. load current 3.324 3.330 3.336 3.342 3.348 3.354 3.360 3.366 3.372 3.378 0.001 0.01 0.1 1 10 load current (a) output voltage (v) dem mode ultrasonic mode pwm mode v in = 12v, tonsel = gnd, en = v in , entrip1 = gnd, entrip2 = 0.91v v out1 output voltage vs. load current 5.048 5.054 5.060 5.066 5.072 5.078 5.084 5.090 5.096 5.102 5.108 5.114 0.001 0.01 0.1 1 10 load current (a) output voltage (v) dem mode ultrasonic mode pwm mode v in = 12v, tonsel = gnd, en = v in , entrip1 = 0.91v, entrip2 = gnd http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 15 ds8223a/b-04 april 2011 www.richtek.com shutdown input current vs. input voltage 8 10 12 14 16 18 20 22 7 9 11 13 15 17 19 21 23 25 input voltage (v) shutdown input current (ua) no load, en = gnd, entrip1 = entrip2 = gnd standby input current vs. input voltage 240 242 244 246 248 250 252 7 9 11 13 15 17 19 21 23 25 input voltage (v) standby input current (ua) no load, en = v in , entrip1 = entrip2 = gnd v ref vs. temperature 1.990 1.993 1.996 1.999 2.002 2.005 2.008 2.011 -50 -25 0 25 50 75 100 125 temperature v ref (v) v in = 12v, entrip1 = entrip2 = gnd, en = v in , tonsel = gnd ( c) v out1 start up time (400 s/div) entrip1 (2v/div) v out1 (5v/div) pgood (10v/div) no load, v in = 12v, tonsel = gnd, en = v in inductor current (2a/div) entrip1 = entrip2 = 0.91v v out1 start up time (400 s/div) entrip1 (2v/div) v out1 (5v/div) pgood (10v/div) heavy load, v in = 12v, tonsel = gnd, en = v in inductor current (2a/div) entrip1 = ntrip2 = 0.91v, i out1 = 4a time (400 s/div) ref (5v/div) vreg3 (5v/div) vreg5 (5v/div) en (10v/div) no load, v in = 12v, tonsel = gnd, en = v in , entrip1 = entrip2 = gnd start up http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 16 ds8223a/b-04 april 2011 www.richtek.com v out2 start up time (400 s/div) entrip2 (2v/div) v out2 (5v/div) pgood (10v/div) no load, v in = 12v, tonsel = gnd, en = v in inductor current (2a/div) entrip1 = entrip2 = 0.91v v out1 delay start time (400 s/div) entrip2 (1v/div) v out1 (5v/div) no load, v in = 12v, tonsel = gnd, en = v in v out2 (5v/div) entrip1 (1v/div) v out2 delay start time (400 s/div) entrip2 (1v/div) v out1 (5v/div) no load, v in = 12v, tonsel = gnd, en = v in v out2 (5v/div) entrip1 (1v/div) v out2 start up time (400 s/div) entrip2 (2v/div) v out2 (5v/div) pgood (10v/div) heavy load, v in = 12v, tonsel = gnd, en = v in inductor current (2a/div) entrip1 = entrip2 = 0.91v v out2 pwm mode load transient response time (20 s/div) ugate2 (20v/div) v out2_ac (50mv/div) lgate2 (10v/div) v in = 12v, tonsel = gnd, en = v in , inductor current (5a/div) skipsel = gnd, i out2 = 0a to 6a v out1 pwm mode load transient response time (20 s/div) ugate1 (20v/div) v out1_ac (50mv/div) lgate1 (10v/div) v in = 12v, tonsel = gnd, en = v in , inductor current (5a/div) skipsel = gnd, i out1 = 0a to 6a http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 17 ds8223a/b-04 april 2011 www.richtek.com power off from entrip1 time (40ms/div) lgate1 (5v/div) ugate1 (20v/div) v out1 (5v/div) entrip1 (1v/div) no load, v in = 12v, tonsel = gnd, en = v in skipsel = gnd ovp time (4ms/div) pgood (5v/div) v out1 (5v/div) no load, v in = 12v, tonsel = gnd, en = v in skipsel = ref v out2 (2v/div) uvp time (20 s/div) v out1 (5v/div) v in = 12v, tonsel = gnd, en = v in skipsel = gnd ugate1 (20v/div) lgate1 (10v/div) inductor current (5a/div) http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 18 ds8223a/b-04 april 2011 www.richtek.com application information the RT8223A/b is a dual, mach response tm drv tm dual ramp valley mode synchronous buck controller. the controller is designed for low voltage power supplies for notebook computers. richtek's mach response tm technology is specifically designed for providing 100ns ? instant-on ? response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. the topology circumvents the poor load-transient timing problems of fixed-frequency c urrent mode pwms while avoiding the problems caused by widely varying switching frequencies in conventional constant on-time and constant off-time pwm schemes. the drv tm mode pwm modulator is specifically designed to have better noise immunity for such a dual output application. the RT8223A/ b includes 5v (vreg5) and 3.3v (vreg3) linear regulators. vreg5 linear regulator can step down the battery voltage to supply both internal circuitry and gate drivers. the synchronous-switch gate drivers are directly powered from vreg5. when vout1 voltage is above 4.66v, an automatic circuit will switch the power of the device from vreg5 linear regulator from vout1. pwm operation the mach response tm drv tm mode controller relies on the output filter capacitor's effective series resistance (esr) to act as a current sense resistor, so the output ripple voltage provides the pwm ramp signal. refer to the RT8223A/b's function block diagram, the synchronous high-side mosfet will be turned on at the beginning of each cycle. after the internal one-shot timer expires, the mosfet will be turned off. the pulse width of this one shot is determined by the converter's input voltage and the output voltage to keep the frequency fairly constant over the input voltage range. another one shot sets a minimum off-time (300ns typ.). the on-time one shot will be triggered if the error comparator is high, the low side switch current is below the current limit threshold, and the minimum off-time one shot has timed out. pwm frequency and on-time control the mach response tm control architecture runs with pseudo-constant frequency by feed forwarding the input and output voltage into the on-time one shot timer. the high-side switch on-time is inversely proportional to the input voltage as measured by the v in , and proportional to the output voltage. there are two benefits of a constant switching frequency. the first is the frequency can be selected to avoid noise sensitive regions such as the 455khz if band. the second is the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. the frequency for 3v smps is set at 1.25 times higher than the frequency for 5v smps. this is done to prevent audio-frequency ? beating ? between the two sides, which switch asynchronously for each side. the frequencies are set by tonsel pin connection as table1. the on-time is given by : on-time = k x (v out / v in ) where ? k ? is set by the tonsel pin connection (table 1). the on-time guaranteed in the electrical characteristics tables are influenced by switching delays in the external high-side power mosfet. two external factors that influence switching-frequency accuracy are resistive drops in the two conduction loops (including inductor and pc board resistance) and the dead-time effect. these effects are the largest contributors to the change of frequency with changing load current. the dead time effect increases the effective on-time, reducing the switching frequency as one or both dead times. it occurs only in pwm mode (skipsel= ref) when the inductor current reverses at light or negative load currents. with reversed inductor current, the inductor's emf causes phasex to go high earlier than normal, extending the on-time by a period equal to the low-to-high dead time. for loads above the critical conduction point, the actual switching frequency is : f = (v out + v drop1 ) / (t on x (v in + v drop1 -v drop2 ) ) where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the resistances in the charging path; and t on is the on-time calculated by the RT8223A/b. http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 19 ds8223a/b-04 april 2011 www.richtek.com table 1. tonsel connection and switching frequency to n sm ps 1 k-factor (us) smps 1 frequency (khz) sm ps 2 k-factor (us) gnd 5 200 4 ref 3.33 300 2.67 vreg5 or vreg3 2.5 400 2 to n sm ps 2 frequency (khz) approximate k-factor error (%) gnd 250 10 ref 375 10 vreg5 or vreg3 500 10 operation mode selection (skipsel) the RT8223A/b supports three operation modes : diode emulation mode, ultrasonic mode, and forced ccm mode. diode-emulation mode (skipsel = gnd) in diode emulation mode, the RT8223A/b automatically reduces switching frequency at light load conditions to maintain high efficiency. this reduction of frequency is achieved smoothly and without increase of v out ripple or load regulation. as the output current decreases from heavy load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. by emulating the behavior of diodes, the low-side mosfet allows only partial of negative current when the inductor free-wheeling current reach negative. as the load current is further decreased, it takes longer and longer to discharge the output capacitor to the level that requires the next ? on ? cycle. the on-time is kept the same as that in the heavy-load condition. in reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous conduction. the transition load point to the light load operation can be calculated as follows (figure 1) : the switching waveforms may appear noisy and asynchronous when light loading causes diode-emulation operation, but this is a normal operating condition that results in high light load efficiency. trade offs in pfm noise vs. light load efficiency are made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load transient response (especially at low input-voltage levels). ultrasonic mode (skipsel = vreg5 or vreg3) connecting skipsel to vreg5 or vreg3 activates a unique diode-emulation mode with a minimum switching frequency of 25khz. this ultrasonic mode eliminates audio-frequency modulation that would otherwise be present when a lightly loaded controller automatically skips pulses. in ultrasonic mode, the low-side switch gate driver signal is or with an internal oscillator (>25khz). once the internal oscillator is triggered, the ultrasonic controller pulls lgatex high, turning on the low side mosfet to induce a negative inductor current. after the output voltage across the ref, the controller turns off the low-side mosfet (lgatex pulled low) and triggers a constant on-time (ugatex driven high). when the on- time has expired, the controller re-enables the low-side mosfet until the controller detects that the inductor current dropped below the zero-crossing threshold. forced ccm mode (skipsel = ref) the low-noise, forced ccm mode (skipsel = ref) disables the zero-crossing comparator, which controls the low side switch on-time. this causes the low side gate driver waveform to become the complement of the high in out load(skip) on (v v ) i t 2l ? ? where ton is the on-time. figure 1. boundary condition of ccm/dcm i l t 0 t on slope = (v in -v out ) / l i l, peak i load = i l, peak / 2 http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 20 ds8223a/b-04 april 2011 www.richtek.com side gate-driver waveform. this in turn causes the inductor current to reverse at light loads as the pwm loop to maintain a duty ratio of v out /v in . the benefit of forced- ccm mode is to keep the switching frequency fairly constant, but it comes at a cost : the no load battery current can be 10ma to 40ma, depending on the external mosfets. reference and linear regulators (ref, vregx) the 2v reference (ref) is accurate within 1% over temperature, making ref useful as a precision system reference. bypass ref to gnd with a 0.22 f (min) capacitor. ref can supply up to 50ua for external loads. loading ref reduces the voutx output voltage slightly because of the reference load regulation error. vreg5 regulator supplies total of 70ma for internal and external loads, including mosfet gate driver and pwm controller. vreg3 regulator supplies up to 70ma for external loads. bypass vreg5 and vreg3 with a 4.7 f (min) capacitor; use an additional 1 f per 5ma of internal and external load. when the 5v main output voltage is above the vreg5 switchover threshold, an internal 1.5 n-mosfet switch connects vout1 to vreg5 while simultaneously shutting down the vreg5 linear regulator. similarly, when the 3.3v main output voltage is above the vreg3 switchover threshold, an internal 1.5 n-mosfet switch connects vout2 to vreg3 while simultaneously shutting down the vreg3 linear regulator. it can decrease the power dissipation from the same battery, because the converted efficiency of smps is better than the converted efficiency of linear regulator. current limit setting (entripx) the RT8223A/b has cycle-by-cycle current limiting control. the current limit circuit employs a unique ? valley ? current sensing algorithm. if the magnitude of the current sense signal at phasex is above the current limit threshold, the pwm is not allowed to initiate a new cycle (figure 2). the actual peak current is greater than the current limit threshold by an amount equal to the inductor ripple current. therefore, the exact current limit characteristic and maximum load capability are a function of the sense resistance, inductor value, battery and output voltage. figure 2. ? valley ? current-limit the RT8223A/b uses the on resistance of the synchronous rectifier as the current sense element. use the worse case maximum value for r ds(on) from the mosfet datasheet, and add a margin of 0.5%/ c for the rise in r ds(on) with temperature. the r ilim resistor between the entripx pin and gnd sets the over current threshold. the resistor r ilim is connected to a 10 a current source from entripx. when the voltage drop across the sense resistor or low side mosfet equals 1/10 the voltage across the r ilim resistor, positive current limit will be activated. the high side mosfet will not be turned on until the voltage drop across the mosfet falls below 1/10 the voltage across the r ilim resistor. choose a current limit resistor by following equation : v ilim = (r ilim x 10 a) / 10 = i ilim x r ds(on) r ilim = (i ilim x r ds(on) ) x 10 / 10 a carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the current sense signal at phasex and gnd. mount or place the ic close to the low side mosfet. mosfet gate driver (ugatex, lgatex) the high side driver is designed to drive high current, low r ds(on) n-mosfet(s). when configured as a floating driver, 5-v bias voltage is delivered from vreg5 supply. the average drive current is also calculated by the gate charge at v gs = 5 v times switching frequency. the instantaneous drive current is supplied by the flying capacitor between bootx and phasex pins. a dead time to prevent shoot through is internally generated between high side mosfet off to low side mosfet on, and low side mosfet off to high side mosfet on. the low side driver is designed to drive high current low r ds(on) n-mosfet(s). the internal pull down transistor i l t 0 i l, peak i lim i load http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 21 ds8223a/b-04 april 2011 www.richtek.com output over voltage protection (ovp) the output voltage can be continuously monitored for over voltage. when over voltage protection is enabled, if the output voltage exceeds 11% of its set voltage threshold, the over voltage protection will be triggered and the lgatex low-side gate drivers will be forced high. this activates the low side mosfet switch, which rapidly discharges the output capacitor and pulls the input voltage downward. RT8223A/b will be latched once ovp is triggered and can only be released by en power-on reset. there is a 10 s delay built into the over voltage protection circuit to prevent false transition. note that lgatex latching high causes the output voltage to dip slightly negative when energy has been previously stored in the lc tank circuit. for loads that cannot tolerate a negative voltage, place a power schottky diode across the output to act as a reverse polarity clamp. if the over voltage condition is caused by a short in high- side switch, turning the low side mosfet on 100% creates an electrical short between the battery and gnd, blowing the fuse and disconnecting the battery from the output. output under voltage protection (uvp) the output voltage can be continuously monitored for under voltage protection. when under voltage protection is enabled, if the output is less than 70% of its set voltage threshold, under voltage protection will be triggered, then both ugatex and lgatex gate drivers are forced low while entering soft-discharge mode. during soft-start, the uvp will be blanked around 3ms. thermal protection the RT8223A/b provides thermal shutdown to prevent the overheat damage. thermal shutdown occurs when the die temperature exceeds +150 c. all internal circuitry shuts down during thermal shutdown. the RT8223A/b triggers thermal shutdown if vregx is not supplied from voutx, while input voltage on vin and drawing current from vregx are too high. even if vregx is supplied from voutx, overloading the vregx causes large power dissipation on automatic switches, which may result in thermal shutdown. soft-start a build-in soft-start is used to prevent surge current from power supply input after entripx is enabled. the typical soft-start duration is 2ms period. furthermore, the maximum allowed current limit is segmented in 5 steps: 20%, 40%, 60%, 80% and 100% during the 2ms period. uvlo protection the RT8223A/b has vreg5 under voltage lock out protection (uvlo). when the vreg5 voltage is lower than 4.2v (typ.) and the vreg3 voltage is lower than 2.5v (typ.), both switch power supplies will be shut off. this is a non-latch protection. power good output (pgood) the pgood is an open-drain type output and requires a pull-up resistor. pgood is actively held low in soft-start, standby, and shutdown. it will be released when both output voltage are above 92.5% of nominal regulation point. the pgood goes low if either output turns off or is 10% below its nominal regulator point. figure 3. reducing the ugatex rise time bootx ugatex phasex 10 v in that drives lgatex low is robust, with a 0.6 typical on- resistance. a 5v bias voltage is delivered from vreg5 supply. the instantaneous drive current is supplied by an input capacitor connected between vreg5 and gnd. for high current applications, some combinations of high and low side mosfets might be encountered that will cause excessive gate-drain coupling, which can lead to efficiency-killing, emi-producing shoot-through currents. this is often remedied by adding a resistor in series with bootx, which increases the turn-on time of the high side mosfet without degrading the turn-off time (figure 3). http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 22 ds8223a/b-04 april 2011 www.richtek.com discharge mode (soft discharge) when entripx is low and a transition to standby, shutdown mode occurs, or the output under voltage fault latch is set, the outputs discharge mode will be triggered. during discharge mode, there is one path to discharge the outputs capacitor residual charge. that is output capacitor discharge to gnd through an internal mos switch. shutdown mode the RT8223A/b smps1, smps2, vreg3 and vreg5 have independent enabling control. drive en, entrip1, entrip2 and enc below the precise input falling edge trip level to place the RT8223A/b in its low power shutdown state. the RT8223A/b consumes only 20 a of input current while in shutdown. power-up sequencing and on/off controls (entripx, enc) entrip1 and entrip2 control smps power-up sequencing. when the RT8223A/b applies in the single channel mode, entrip1 or entrip2 enables the respective outputs when entripx voltage rises above 0.4v. furthermore, the RT8223A/b applies in the dual channel mode. enc enables the outputs when enc voltage rises above 2v. if both of entrip1 and entrip2 become higher than the enable threshold voltage at a different time (without 60 s), one can force the latter one output starts after the former one regulates. output voltage setting (fbx) connect fbx directly to gnd or vreg5 to enable the fixed, smps output voltages (3.3v and 5v). connect a resistor voltage divider at the fbx between the voutx and gnd to adjust the respective output voltage between 2v and 5.5v (figure 4). choose r2 to be approximately 10k , and solve for r1 using the equation : outx fbx r1 v = v 1 r2 ?? ?? + ?? ?? ?? ?? where v fbx is 2v (typ.). vreg5 connects to vout1 through an internal switch only when vout1 is above the vreg5 automatic switch threshold (4.66v). vreg3 connects to vout2 through an internal switch only when vout2 is above the vreg3 automatic switch threshold (3v). this is the most effective way when the fixed output voltages are used. once vregx is supplied from voutx, the internal linear regulator turns off. this reduces internal power dissipation and improves efficiency when the vregx is powered with a high input voltage. figure 4. setting voutx with a resistor-divider output inductor selection the switching frequency (on-time) and operating point (% ripple or l ir ) determine the inductor value as shown as follows : on in outx ir load(max) t(v v ) l = li ? where l ir is the ratio of the peak to peak ripple current to the average inductor current. find a low loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ) : i peak = i load(max) + [(l ir / 2) x i load(max) ] this inductor ripple current also impacts transient-response performance, especially at low vin ? voutx differences. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the peak amplitude of the output transient v sag is also a function of the output transient. the v sag also features a function of the phasex lgatex r1 r2 v outx v in ugatex voutx fbx gnd pgnd http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 23 ds8223a/b-04 april 2011 www.richtek.com sw esr out f 1 f = 2 esr c 4 output capacitor stability stability is determined by the value of the esr zero relative to the switching frequency. the point of instability is given by the following equation : do not put high-value ceramic capacitors directly across the outputs without taking precautions to ensure stability. large ceramic capacitors can have a high- esr zero frequency and cause erratic, unstable operation. however, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting voutx or the fbx divider close to the inductor. unstable operation manifests itself in two related and distinctly different ways: double pulsing and feedback loop instability. double pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this ? fools ? the error comparator into triggering a new cycle immediately after the 300ns minimum off-time period has expired. double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it may indicate the possible presence of loop instability, which is caused by insufficient esr. loop instability can result in oscillations at the output after line or load perturbations that can trip the overvoltage protection latch or cause the output voltage to fall below the tolerance limit. the easiest method for checking stability is to apply a very fast zero to max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. it helps to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step response under or overshoot. thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow p-p load(max) v esr i p-p ir load(max) v esr li in non-cpu applications, the output capacitor's size depends on how much esr is needed to maintain an acceptable level of output voltage ripple : where v p-p is the peak to peak output voltage ripple. organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. for low input to output voltage differentials (vin / voutx < 2), additional output capacitance is required to maintain stability and good efficiency in ultrasonic mode. the amount of overshoot due to stored inductor energy can be calculated as : 2 peak soar out outx (i ) l v 2c v 2 outx load off(min) in sag in outx out outx off(min) in v (i ) l k t v v = vv 2c v k t v ?? ? + ?? ?? ?? ? ?? ? ?? ?? ?? ?? where minimum off-time (t off(min) ) = 300ns (typ.) and k is from table 1. output capacitor selection the output filter capacitor must have low enough esr to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. also, the capacitance value must be high enough to absorb the inductor energy going from a full load to no load condition without tripping the ovp circuit. for cpu core voltage converters and other applications where the output is subject to violent load transients, the output capacitor's size depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance : maximum duty factor, which can be calculated from the on-time and minimum off-time : where i peak is the peak inductor current. http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 24 ds8223a/b-04 april 2011 www.richtek.com and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT8223A/b, the maximum junction temperature is 125 c. the junction to ambient thermal resistance ja is layout dependent. for wqfn-24l 4x4 package, the thermal resistance ja is 52 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (52 c/w) = 1.923w for wqfn-24l 4x4 package the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT8223A/b package, the figure 5 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. figure 5. derating curve for RT8223A/b package 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) four layers pcb wqfn-24l 4x4 layout considerations layout is very important in high frequency switching converter design. if the ic is designed improperly, the pcb could radiate excessive noise and contribute to the converter instability. certain points must be considered before starting a layout using the RT8223A/b. ` place the filter capacitor close to the ic, within 12 mm (0.5 inch) if possible. ` keep current limit setting network as close as possible to the ic. routing of the network should avoid coupling to high voltage switching node. ` connections from the drivers to the respective gate of the high side or the low side mosfet should be as short as possible to reduce stray inductance. use 0.65- mm (25 mils) or wider trace. ` all sensitive analog traces and components such as voutx, fbx, gnd, entripx, pgood, and tonsel should be placed away from high voltage switching nodes such as phasex, lgatex, ugatex, or bootx nodes to avoid coupling. use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. ` gather ground terminal of vin capa citor(s), voutx capacitor(s), and source of low side mosfets as close as possible. pcb trace defined as phasex node, which connects to source of high side mosfet, drain of low side mosfet and high voltage side of the inductor, should be as short and wide as possible. http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 25 ds8223a/b-04 april 2011 www.richtek.com table 3. power up sequencing en (v) enc (v) entrip1 (v) entrip2 (v) vreg 5 vreg3 smps1 smps2 low low x x off off off off ?>1v? => high low x x on (after ref powers up) on (after ref powers up) off off ?>1v? => high ?>2v? => high low low on (after ref powers up) on (after ref powers up) off off ?>1v? => high ?>2v? => high low high on (after ref powers up) on (after ref powers up) off on ?>1v? => high ?>2v? => high high (after entrip2 is high without 60 s) high on (after ref powers up) on (after ref powers up) on (after smps2 on) on ?>1v? => high ?>2v? => high high low on (after ref powers up) on (after ref powers up) on off ?>1v? => high ?>2v? => high high high (after entrip 1 i s hi gh without 60 s) on (after ref powers up) on (after ref powers up) on on (after smps1 on) ?>1v? => high ?>2v? => high high high on (after ref powers up) on (after ref powers up) on on table 2. operation mode truth table mode test condition comment power-up vregx < uvlo threshold transitions to discharge mode after a vin por and after ref becomes valid. vreg5, vreg3, and ref remain active. run en = high, vout1 or vout2 enabled normal operation. over voltage prote ction either output > 111% of the nominal level. lgatex is forced high. vreg3, vreg5 active. exited by vin por or by toggling en, entripx under voltage prote ction either output < 70% of the nominal level after 3ms time-out expires and output is enabled both ugatex and lgat ex are forced low and enter discharge mode. vreg3, vreg5 active. exited by vin por or by toggling en, entripx, enc discharge either smps output is still high in either standby mode or shutdown mode during discharge mode, there is one path to discharge the outputs capacitor residual charge. that is output capacitor discharge to gnd through an internal switch. standby enc < startup threshold, en = high. vreg3, vreg5 active. shutdown e n = lo w all circuitry of f. thermal shutdown tj > +150c all circuitry off. exit by vin por or by toggling en, entripx, enc http://www..net/ datasheet pdf - http://www..net/
RT8223A/b 26 ds8223a/b-04 april 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a a1 a3 d e d2 e2 l b e 1 see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 3.950 4.050 0.156 0.159 d2 2.300 2.750 0.091 0.108 e 3.950 4.050 0.156 0.159 e2 2.300 2.750 0.091 0.108 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 24l qfn 4x4 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2 http://www..net/ datasheet pdf - http://www..net/

▲Up To Search▲

Price & Availability of RT8223A

	To Download RT8223A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .